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Current Result Document :
ÇѱÛÁ¦¸ñ(Korean Title) |
¸ÖƼÄÚ¾î ȯ°æÀÇ In-Memory µ¥ÀÌÅͺ£À̽º »ó¿¡¼ È¿À²ÀûÀÎ Æ®·£Àè¼Ç 󸮸¦ À§ÇÑ Ãæµ¹ ¿¹Ãø ±â¹Ý Æ®·£Àè¼Å³Î ¸Þ¸ð¸® ±â¹ý |
¿µ¹®Á¦¸ñ(English Title) |
Conflict Prediction based Transactional Memory Technique for Efficient Transaction Processing in Multi-core In-Memory Databases |
ÀúÀÚ(Author) |
À±¹Î
°¹®È¯
À忬¿ì
ÀåÀç¿ì
Yoon Min
Mun-Hwan Kang
Yeon-Woo Jang
Jae-Woo Chang
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¿ø¹®¼ö·Ïó(Citation) |
VOL 33 NO. 02 PP. 0163 ~ 0179 (2017. 08) |
Çѱ۳»¿ë (Korean Abstract) |
ÃÖ±Ù Intel¿¡¼ óÀ½À¸·Î »ó¿ëÈµÈ Hardware Transactional Memory(HTM)·Î½á Transactional Synchronization Extension(TSX)¸¦ Á¦¾ÈÇÏ¿´´Ù. HTMÀº Æ®·£Àè¼Ç 󸮸¦ À§ÇÑ º´·Ä ÇÁ·Î±×·¡¹Ö Æз¯´ÙÀÓÀ»Å©°Ô ¹Ù²Ù¾úÀ¸¸ç, À̸¦ ÀÌ¿ëÇÑ ´Ù¼öÀÇ ¿¬±¸µéÀÌ Á¦¾ÈµÇ¾ú´Ù. ±×·¯³ª, ±âÁ¸ ¿¬±¸µéÀº ´Ù¾çÇÑ ¿öÅ©·Îµå¿¡ ´ëÇØ È¹ÀÏÈµÈ È¯°æÀ» Á¦°øÇÏ´Â ¹®Á¦Á¡ÀÌ Á¸ÀçÇÑ´Ù. µû¶ó¼ ÀÌ·¯ÇÑ ¹®Á¦Á¡À» ÇØ°áÇϱâ À§ÇØ, º» ³í¹®¿¡¼´Â ¸ÖƼÄÚ¾î Àθ޸𸮠ȯ°æ¿¡¼ÀÇ È¿À²ÀûÀÎ Æ®·£Àè¼Ç 󸮸¦ À§ÇÑ Ãæµ¹ ¿¹Ãø ±â¹Ý Æ®·£Àè¼Å³Î ¸Þ¸ð¸® ±â¹ýÀ» Á¦¾ÈÇÑ´Ù. Á¦¾ÈÇÏ´Â Ãæµ¹ ¿¹Ãø ±â¹Ý Æ®·£Àè¼Å³Î ¸Þ¸ð¸® ±â¹ýÀº Ãæµ¹ ¿¹ÃøÀ» À§ÇÑ ¸ÅÆ®¸¯½º¸¦ ±¸¼ºÇϸç, °¢ Æ®·£Àè¼Ç¿¡ ´ëÇÑ ¸ÞŸµ¥ÀÌÅ͸¦ ÃàÀûÇÏ°í, ´Ù¾çÇÑ Æ®·£Àè¼ÇÀÇ abort ºÐ¼®À» ÅëÇÑ Ãæµ¹ ¿¹ÃøÀ» Á¦°øÇÑ´Ù. À̸¦ ÅëÇØ Æ®·£Àè¼ÇÀÇ Ãæµ¹ ¿¹ÃøÀ» ¼öÇàÇÏ¿© ÃÖ»óÀÇ ¼º´ÉÀ» º¸ÀåÇÏ´Â HTM ¹× Á÷·Ä ½ÇÇàÀ» ¼öÇàÇÔÀ¸·Î½á, ¸ÖƼ ÄÚ¾î ȯ°æ¿¡¼ Æ®·£Àè¼Ç ó¸® È¿À²À» Çâ»ó½ÃŲ´Ù. ¾Æ¿ï·¯, °æ»çÇÏ°¹ý ±â¹Ý jump ¾Ë°í¸®Áò ¹× Æ®·£Àè¼Ç ÇÊÅ͸µ ±â¹ýÀ» ÅëÇØ °¢ ¿öÅ©·Îµå ³»¿¡¼ Æ®·£Àè¼ÇÀÇ Æ¯¼ºÀ» ¹Ý¿µÇÑ È¿À²ÀûÀÎ HTM Àç½Ãµµ Á¤Ã¥À» Á¦°øÇÑ´Ù. ¸¶Áö¸·À¸·Î STAMP¸¦ ÅëÇÑ ¼º´ÉÆò°¡¸¦ ÅëÇØ, Á¦¾ÈÇÏ´Â ±â¹ýÀÌ ±âÁ¸ ±â¹ý¿¡ ºñÇØ 50-200%ÀÇ ¼º´É Çâ»óÀ» ´Þ¼ºÇÔÀ» º¸ÀδÙ.
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¿µ¹®³»¿ë (English Abstract) |
Recently, Intel proposed Transactional Synchronization Extension (TSX) as its first mainstream Hardware Transactional Memory (HTM), HTM has greatly changed the parallel programming paradigm for transaction processing. As a result, a number of studies on HTM have been actively done. However, the existing studies have a problem that they provide a static HTM configuration for all workloads. To solve the problem, we propose a hardware transactional memory scheme based on conflict prediction for efficient transaction processing in multi-core in-memory environments. First, the proposed HTM scheme constructs a matrix for conflict prediction, collects metadata about transactions, and provide conflict prediction through the analysis of various transactions aborts. As a result, the proposed HTM scheme improves the efficiency of transaction processing in multi-core in-memory environments by performing the conflict prediction of transactions. In addition, the proposed scheme provides an efficient HTM retry policy according to the characteristic of a given workload by using a jump algorithm based on gradient descent exploration. Finally, it is shown through our performance analysis using STAMP that the proposed scheme achieves about 50~200% better performance than the existing HTM schemes.
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Å°¿öµå(Keyword) |
Çϵå¿þ¾î Æ®·£Àè¼Å³Î ¸Þ¸ð¸®
Ãæµ¹ ¿¹Ãø
Àç½Ãµµ Á¤Ã¥
¸ÖƼÄÚ¾î Àθ޸𸮠ȯ°æ
Hardware Transactional Memory
conflict prediction
retry policy
multi-core in-memory database
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